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Introducing Parker, NVIDIA’s Newest SOC for Autonomous Vehicles

NVIDIA today took the cloak off Parker, our newest mobile processor that will power the next generation of autonomous vehicles.

Get Under the Hood of Parker, Our Newest SOC for Autonomous Vehicles

Get Under the Hood of Parker, Our Newest SOC for Autonomous Vehicles

Speaking at the Hot Chips conference in Cupertino, California, we revealed the architecture and underlying technology of this highly advanced processor, which is ideally suited for automotive applications like self-driving cars and digital cockpits.

You may recall we mentioned Parker at CES earlier this year, when we introduced the NVIDIA DRIVE PX 2 platform (shown above). That platform uses two Parker processors and two Pascal architecture-based GPUs to power deep learning applications. More than 80 carmakers, tier 1 suppliers and university research centers around the world are now using our DRIVE PX 2 system to develop autonomous vehicles. This includes Volvo, which plans to road test DRIVE PX 2 systems in XC90 SUVs next year.

Parker diagramForging a Future for Automotive

Parker delivers class-leading performance and energy efficiency, while supporting features important to the automotive market such as deep learning, hardware-level virtualization for tighter design integration, a hardware-based safety engine for reliable fault detection and error processing, and feature-rich IO ports for automotive integration.

Built around NVIDIA’s highest performing and most power-efficient Pascal GPU architecture and the next generation of NVIDIA’s revolutionary Denver CPU architecture, Parker delivers up to 1.5 teraflops(1) of performance for deep learning-based self-driving AI cockpit systems.

Need for Speed

Parker delivers 50 to 100 percent higher multi-core CPU performance than other mobile processors(2). This is thanks to its CPU architecture consisting of two next-generation 64-bit Denver CPU cores (Denver 2.0) paired with four 64-bit ARM Cortex A57 CPUs. These all work together in a fully coherent heterogeneous multi-processor configuration.

The Denver 2.0 CPU is a seven-way superscalar processor supporting the ARM v8 instruction set and implements an improved dynamic code optimization algorithm and additional low-power retention states for better energy efficiency. The two Denver cores and the Cortex A57 CPU complex are interconnected through a proprietary coherent interconnect fabric.

A new 256-core Pascal GPU in Parker delivers the performance needed to run advanced deep learning inference algorithms for self-driving capabilities. And it offers the raw graphics performance and features to power multiple high-resolution displays, such as cockpit instrument displays and in-vehicle infotainment panels.

Scalable Architecture

Working in concert with Pascal-based supercomputers in the cloud, Parker-based self-driving cars can be continually updated with newer algorithms and information to improve self-driving accuracy and safety.

Parker includes hardware-enabled virtualization that supports up to eight virtual machines. Virtualization enables carmakers to use a single Parker-based DRIVE PX 2 system to concurrently host multiple systems, such as in-vehicle infotainment systems, digital instrument clusters and driver assistance systems.

Parker is also a scalable architecture. Automakers can use a single unit for highly efficient systems. Or they can integrate it into more complex designs, such as NVIDIA DRIVE PX 2, which employs two Parker chips along with two discrete Pascal GPU cores.

In fact, DRIVE PX 2 delivers an unprecedented 24 trillion deep learning operations per second to run the most complex deep learning-based inference algorithms. Such systems deliver the supercomputer level of performance that self-driving cars need to safely navigate through all kinds of driving environments.

parker_specifications_two

Parker Specifications

To address the needs of the automotive market, Parker includes features such as a dual-CAN (controller area network) interface to connect to the numerous electronic control units in the modern car, and Gigabit Ethernet to transport audio and video streams. Compliance with ISO 26262 is achieved through a number of safety features implemented in hardware, such as a safety engine that includes a dedicated dual-lockstep processor for reliable fault detection and processing.

Parker is architected to support both decode and encode of video streams up to 4K resolution at 60 frames per second. This will enable automakers to use higher resolution in-vehicle cameras for accurate object detection, and 4K display panels to enhance in-vehicle entertainment experiences.

Expect to see more details on Parker’s architecture and capabilities as we accelerate toward making the self-driving car a reality.

  1. References the native FP16 (16-bit floating-point) processing capability of Parker.
  2. Based on SpecINT2K-Rate performance measured on Parker development platform and devices based on competing mobile processors.

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My name is Sayed Ahmadreza Razian and I am a graduate of the master degree in Artificial intelligence .
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Related topics such as image processing, machine vision, virtual reality, machine learning, data mining, and monitoring systems are my research interests, and I intend to pursue a PhD in one of these fields.

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